RDMA Line Controller

We are looking for a driven Line Controller / Business Controller with around 5 years of experience to join an international biopharmaceutical company experiencing strong growth. This is a perfect opportunity for a controller who is ready for a natural next step in their career, combining hands-on line controlling with finance business partnering in a complex global organization. We review applications continuously, so do not hesitate to apply today! About the role Our client is looking for a dedicated Line Controller to take on a central and business-facing role within Research, Development and Medical Affairs (RDMA). The organization manages an annual budget of several billion SEK, divided between project activities and the ongoing line organization, comprising approximately 200 employees and 100 cost centers across Europe, the US, and Japan. In this role, you will act as a financial business partner to several functional line leaders, translating business plans into financial realities and creating transparency around performance. This is a dynamic role suited for someone who wants to combine qualified finance business partnering with clear operational line responsibility (budgeting, forecasting, cost center management, and variance analysis) in a global environment. You are offered A natural career step: A role where you get full ownership of your areas and room to grow in a global biopharmaceutical environment. A strong international network: Collaborate closely with global functional leaders, international co-controllers, and an experienced finance team. Strategic and operational variety: A highly varied role where you move seamlessly between forecasting discussions with functional leaders and hands-on Excel analysis, cost center management, and follow-ups Work tasks Your responsibilities will include: Act as a financial business partner to functional leaders and senior stakeholders within RDMA. Develop a thorough understanding of business plans, priorities, resource requirements, and cost drivers. Constructively challenge budget owners' assumptions and plans, helping to identify practical solutions that balance scientific needs with available resources. Drive the four annual planning and forecasting cycles, including the budget process. Coordinate and quality-assure financial input from a large number of cost centers and business areas. Monitor actual performance against budget/forecast and analyze the underlying causes of variances. Identify financial risks and opportunities, explaining their impact on the full-year forecast. Take ownership of relevant month-end and quarter-end close activities (accruals, reallocations, and closing documentation). Collaborate with accounting, Business Controllers, System Controllers, and the wider global finance organization to improve processes and transparency. We are looking for Around 4-6 years of relevant experience in Business Controlling, Line Controlling, or Finance Business Partnering. Experience with budgeting, forecasting, financial planning, and performance management. Have a solid understanding of month-end closing, accruals, and other accounting-related controlling activities. Have strong analytical capabilities and advanced Excel skills. Fluency in English in both written and spoken. It is meritorious if you have Fluency in Swedish both written and spoken. Experience in the life science pharmaceutical, research, or other knowledge-intensive industries. Experience in R&D controlling. Experience in providing financial support and guidance to teams or organizations working with clinical studies. Experience with large ERP systems, financial reporting tools, or digital/AI-enabled automation in finance. To succeed in the role, your personal skills are: Structured Proactive Driven Communicative team payer Social Our recruitment process This recruitment process is handled by Academic Work and it is our client’s wish that all questions regarding the position is directed to Academic Work. Our selection process is continuous and the advert may close before the recruitment process is completed if we have moved forward to the next phase. The process includes two tests: one personality test and one cognitive test. The tests are tools to find the right talent for the right position, to enable equality, diversity, and a fair process.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com [http://www.asteralabs.com/]. DISTINGUISHED ASIC DESIGN ENGINEER/ SENIOR PRINCIPAL Location: Germany (on-site) ROLE OVERVIEW Astera Labs is building purpose-built silicon for rack-scale AI infrastructure. As a Distinguished Engineer, you will be a senior technical leader driving ASIC design for next-generation Ethernet and Scale-Up (ESUN) connectivity products. You will set technical direction across the full ASIC design flow, spanning high-speed Ethernet, UALink, UCIe, and PCIe Gen 6/7. You will solve complex scale-up networking challenges, mentor senior engineers, and turn ambitious product goals into robust, manufacturable silicon. TECHNICAL LEADERSHIP & ARCHITECTURE * Define and drive ASIC architecture for Ethernet/ESUN connectivity products across UALink, UCIe, PCIe Gen 6/7, and Ethernet. * Lead architecture and microarchitecture for high-performance Ethernet controllers, MACs, NIC datapaths, packet processing pipelines, and AI interconnect fabrics. * Define scalable, low-latency, high-bandwidth data movement, scheduling, buffering, congestion management, QoS, reliability, and flow control. * Architect hardware acceleration for NIC functions, RDMA, DMA, virtualization, and protocol offloads. * Lead tradeoff analysis across performance, power, area, latency, scalability, resiliency, and programmability. * Serve as a technical authority across digital, networking, and system domains. ASIC DESIGN & EXECUTION * Lead RTL design and microarchitecture development for Ethernet controllers, MACs, NIC datapaths, protocol engines, and AI networking subsystems. * Design packet processing architectures, DMA engines, queue management, scheduling, buffering, and memory subsystem interfaces. * Develop hardware mechanisms for RDMA, zero-copy data movement, congestion control, transport reliability, and protocol acceleration. * Design scalable architectures supporting virtualization, multi-tenant isolation, traffic management, and quality of service. * Partner with firmware and software teams to define hardware/software interfaces for initialization, management, telemetry, performance monitoring, and diagnostics. * Drive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up. * Partner cross-functionally to meet performance, timing, power, area, manufacturability, and reliability targets. BASIC QUALIFICATIONS * Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field. * 15+ years of ASIC/SoC design experience, with a track record of delivering complex, high-speed networking or connectivity silicon from architecture through production. * Deep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs. * Extensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems. * Strong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies. * Experience designing hardware for packet parsing, scheduling, buffering, DMA, queue management, flow control, congestion management, and transport acceleration. * Strong understanding of high-speed interconnects and protocols, including Ethernet, PCIe, and AI scale-up fabrics. * Hands-on experience across the complete ASIC development flow, including architecture, RTL design, integration, synthesis, timing closure, physical implementation, tapeout, and post-silicon validation. * Demonstrated technical leadership across multiple teams and product programs. PREFERRED QUALIFICATIONS * Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline. * Direct experience with UALink, UCIe, PCIe Gen 6/7, and/or advanced Ethernet architectures and protocols. * Experience designing Ethernet MACs, controllers, SmartNICs, DPUs, NICs, switch datapaths, or packet processing engines. * Experience developing Ethernet-based scale-up networking solutions for AI and HPC systems. * Experience leading architecture or design for multiple successful advanced-node ASIC tapeouts. * Excellent communication, collaboration, and mentorship skills.   We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.