Digital IC Backend Design Engineer

Arago

MEET ARAGO AND THE ARAGONIANS Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors. Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs. Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles: 1. Do great things: we deliver work we’re proud to sign our name to. 2. High velocity: speed matters. We move quickly, one step at a time. 3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie. Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders. WHAT YOU’LL DO Design high-performance analog and RF ICs optimized for precision, power, and area, driving Arago’s prototype and product iterations from architecture to silicon validation. RESPONSIBILITIES * Design and simulate analog and RF integrated circuits, including critical blocks such as amplifiers, mixers, PLLs, ADCs, DACs, and bias/reference circuits, with a focus on signal integrity, linearity, and precision. * Optimize circuits for power, area, and performance trade-offs, ensuring designs meet system-level requirements across process, voltage, and temperature (PVT) variations. * Collaborate closely with optics, simulation and PCB teams to define architecture and block-level specifications for Arago’s successive prototypes and product iterations, ensuring tight alignment with overall performance and integration goals. * Work with layout engineers to guide floor-planning and physical design, minimizing parasitic effects and preserving analog precision in layout-sensitive blocks. * Support post-silicon validation and bring-up, defining test plans, analyzing lab measurements, and correlating results with simulation to refine future design iterations. * Language: English at a proficient level. French is a plus. REQUIRED SKILLS AND EXPERIENCE * A sound mathematical understanding and deep physical intuition of analog electronics, as well as analog voltage-to-current and current-to-voltage conversion at low and high frequencies. * Experience in designing high-precision analog systems for signal processing or power electronics. Experience working with high-frequency analog signals is valued. * Extensive experience in IC design and post-layout design methodology using standard industry tools like Cadence Virtuoso. * Proficiency in designing and optimizing mixed-signal circuits, including DACs and ADCs at low (kHz-MHz) and high (>GHz) frequencies, and signal conditioning circuits, ensuring flawless integration between analog RF components and digital processors. * Strong understanding of signal integrity, crosstalk, and noise reduction techniques in mixed-signal environments, particularly in high-frequency RF systems interfacing with digital processors. * Advanced node experience required (<28nm). PAY AND BENEFITS * Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions. * Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers). * Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location. * Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays. * Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive. * Reimbursement of 50% of the public transport subscription fee. * A high-paced, multicultural (with 9 nationalities), and engineering-led environment.

Arago

MEET ARAGO AND THE ARAGONIANS Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors. Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs. Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles: 1. Do great things: we deliver work we’re proud to sign our name to. 2. High velocity: speed matters. We move quickly, one step at a time. 3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie. Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders. WHAT YOU’LL DO Play a critical role in ensuring the functional integrity, performance, and reliability of next-generation optical chips. REQUIRED SKILLS AND EXPERIENCE * Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field. * Proven fluency and hands-on expertise in SystemVerilog for verification. * Demonstrated prior experience with the UVM framework and modern verification environments. * Direct knowledge of standard protocols (AXI/AXIStream, APB/AHB, I2C, JTAG, PCIe) and experience verifying digital logic for high-speed interfaces. * Practical experience verifying RISC-V CPU designs or equivalent digital processor architectures within an ASIC context. * Strong analytical and communication skills for customer-driven projects and interdisciplinary teamwork. * Language: English at a proficient level. French is a plus. RESPONSIBILITIES * Develop robust verification plans for complex digital and mixed-signal optical chip designs. * Collaborate closely with architects, designers, and customers to understand logic requirements, translate them into verification strategies, and deliver clear, actionable feedback throughout the development process. * Perform netlist-level simulations with SDF back-annotation for timing-accurate verification * Support FPGA/ASIC bring-up and post-silicon validation as needed * Develop, maintain, and optimize testbenches and verification components using advanced SystemVerilog features, such as constrained random testing, assertions, and transaction-level modeling, to create robust coverage-driven environments. * Design scalable, reusable UVM-based environments and components (e.g., agents, monitors, scoreboards) for block- and system-level verification. Employ UVM to achieve regression automation, functional coverage closure, and high bug-detection efficiency. * Develop and execute verification strategies for digital blocks implementing or interfacing with PCI Express (PCIe). Apply protocol-checking, compliance validation, error injection, and debug skills for PCIe endpoints and root complex devices. Use protocol analyzers and simulation environments to validate correct implementation across all protocol layers. * Participate in the verification of RISC-V CPU cores and subsystems. Create test plans targeting processor modules (ALU, decoder, register file, control logic), with reference model comparisons, signature checks, and coverage of edge-case scenarios. Leverage formal verification and compliance suites for thorough design validation. * Plan and perform end-to-end ASIC verification, from block-level testbenches to full-chip integration. Execute functional and regression tests, formal verification, and coverage analysis. Debug and resolve design issues, ensuring pre-silicon reliability before manufacturing. Engage in design reviews and system-level protocol validation with cross-functional teams. DESIRED ATTRIBUTES * Proactive in anticipating and mitigating design risks, including the assessment of undetected flaws via coverage-driven and formal verification. * Proven ability to deliver in fast-paced, collaborative startup environments. * Ownership mindset, attention to detail, and commitment to high product quality. PAY AND BENEFITS * Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions. * Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers). * Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location. * Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays. * Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive. * Reimbursement of 50% of the public transport subscription fee. * A high-paced, multicultural (with 10 nationalities), and engineering-led environment. OUR HIRING PROCESS: YOUR JOURNEY TO ARAGO * Screening Call : Get to know you beyond your CV. * Technical meeting : Deep dive into your past projects and technical achievements. * CEO Interview : Assess the fit with the team’s culture and long-term vision. * Reference Calls: Mandatory calls with your former managers to validate strengths, weaknesses, and work style. * Technical Assessment: Take-home technical assignment crafted to the role you’re applying for. * Final Interview : Discuss your technical assignment and address any remaining questions with team members.

Arago

MEET ARAGO AND THE ARAGONIANS Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors. Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs. Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles: 1. Do great things: we deliver work we’re proud to sign our name to. 2. High velocity: speed matters. We move quickly, one step at a time. 3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie. Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders. WHAT YOU’LL DO Work on the definition and realization of next-generation compute architectures by driving system-level design, guiding cross-functional engineering teams, and delivering silicon from first concept to production. RESPONSIBILITIES * Carry the top-level architecture of Arago’s multiphysics compute platform, including processing elements, interconnects, memory subsystems, and system-level control. * Own the architectural vision from concept through tape-out, driving system modeling, specification, and implementation handoff across engineering teams. * Work and mentor cross-functional hardware teams across RTL design, functional verification, and physical integration to ensure consistent technical direction and execution quality. * Collaborate with software, packaging, and system integration teams to ensure architectural choices support overall platform scalability, performance, and reliability. * Evaluate new architectural directions, develop performance and cost models, and guide prototyping efforts to de-risk innovations for future product generations. REQUIRED SKILLS AND EXPERIENCE * Proven track record in architecting complex, high-performance digital systems such as multicore processors, vector engines, and domain-specific accelerators. * Deep expertise in computer architecture, including memory hierarchies, interconnects, cache coherence, instruction set design, and performance-power-area trade-offs. * Hands-on experience with the design and integration of compute-intensive blocks such as vector arithmetic logic units (ALUs), SIMD pipelines, systolic arrays, and custom datapaths for signal or tensor processing. * Experience in leading full ASIC development cycles from architectural concept and modeling through RTL implementation, functional verification, physical design, and tape-out. * Experience with advanced system integration and packaging technologies such as HBM, chiplets, and 2.5D/3D integration, with a strong understanding of their architectural and system-level impact, is highly valued. * Strong leadership and communication skills, with the ability to align multidisciplinary teams (architecture, RTL, verification, software, and physical design) under a unified vision. PAY AND BENEFITS * Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions. * Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers). * Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location. * Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays. * Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive. * A high-paced, multicultural (with 9 nationalities), and engineering-led environment.