Senior Firmware Validation Engineer

ABOUT US Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. JOB SUMMARY We are seeking a Senior System Validation Engineer to design and implement validation tests for Arm-based data center SoCs using a combination of open-source benchmarking tools and custom micro-benchmarks. Define test cases, tune workload parameters, and use Python to automate and analyze validation across processing units, system memory, communication links, and PCI Express components.   THE TEAM The Systems Validation team validates Graphcore’s AI compute platforms across hardware, firmware, and software domains. RESPONSIBILITIES AND DUTIES * Translate hardware features into structured, parameterized test cases, including: * Objectives, workload models, parameters, metrics, and pass/fail criteria.  * Use and tune open-source tools such as: * Stress-ng, fio, iperf, sysbench, Imbench * Define workload parameters: * Concurrency (threads/cores), memory footprint, access patterns * Queue depth, block size, CPU/NUMA affinity.  * Design and execute validation scenarios: * Functional, performance, stress, and corner-case testing. * Validate across domains: * CPU scaling and cache behavior * Memory (DDR/HBM) bandwidth, latency, and NUMA effects * Interconnect contention under multi-core load * PCIe/I-O throughput, latency, and multi-device scenarios * Develop custom micro-benchmarks (C/C++) when existing tools are insufficient * Use Python to: * Automate test execution and orchestration * Implement parameter sweeps and test matrices  * Parse, analyze, and visualize results.  * Debug system behavior and performance issues in collaboration with hardware and firmware teams CANDIDATE PROFILE Essential: * Strong background in Linux systems and low-level performance analysis * Experience in system validation, benchmarking, or performance testing * Solid understanding of one or more domains: * CPU architecture, memory systems, or PCIe * Experience using benchmarking tools (stress-ng, fio, iperf, etc.) * Ability to define test cases, parameters, and workload models * Proficiency in Python (essential) for automation, orchestration, and data analysis * Programming experience in C/C++ for micro-benchmark development DESIRABLE: * Experience with Arm-based platforms * Strong programming skills in C/C++ and Python for system-level development and automation * Familiarity with performance tools (perf, numactl, taskset) * Experience with large-scale or high core-count systems   USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Job Summary Reporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms. The role will focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams to ensure robust memory subsystem functionality, performance and reliability. The successful candidate will take ownership of significant validation activities, contribute to debug and root-cause analysis efforts, and help improve validation methodologies, automation and infrastructure. The Team The Memory Validation team sits within the Validation organisation and is responsible for the bring-up, validation, characterization and debug of memory subsystems across Graphcore silicon and platform products. The team supports DDR and HBM validation activities throughout the product lifecycle, from first silicon through production readiness. Engineers work closely with architecture, RTL, firmware, characterization, systems and platform teams to ensure memory technologies meet functionality, performance, reliability and performance objectives. Responsibilities and Duties * Execute validation and bring-up activities for DDR and HBM memory subsystems  * Verify memory bring-up software, firmware and scripts against defined project requirements  * Debug firmware, hardware and system-level issues and contribute to root-cause analysis activities  * Analyse system logs, validation data and characterization results to identify failures and performance issues  * Perform PHY characterization and analog-level analysis during stress testing and validation activities  * Develop and execute functional, stress, performance and corner-case validation tests  * Perform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation  * Characterize memory bandwidth, latency, training behaviour and subsystem stability across operating conditions  * Develop Python-based automation, test infrastructure and reporting tools to improve validation efficiency  * Collaborate with architecture, RTL, firmware and platform teams to investigate and resolve technical issues  * Contribute to memory subsystem debug activities spanning silicon, firmware, board and system domains  * Support development of validation methodologies, debug procedures and reporting frameworks  * Contribute to continuous improvement of validation infrastructure and engineering processes  * Support silicon characterization, production readiness and qualification activities  * Document validation results and communicate findings to the wider engineering team  Candidate Profile Essential * Strong experience validating DDR, LPDDR, HBM or related DRAM technologies  * Deep understanding of DRAM architecture, memory subsystem operation and memory controller functionality  * Experience with firmware, BIOS and Embedded C development  * Strong programming skills in C and Python  * Hands-on experience using laboratory equipment including oscilloscopes and related measurement instrumentation  * Experience interfacing with low-speed peripherals including GPIO, SPI, I2C and UART/serial interfaces  * Experience performing functional testing and signal measurements including voltage, frequency and timing analysis  * Strong knowledge of embedded systems and microcontroller-based platforms  * Hands-on experience with board bring-up and hardware validation activities  * Experience debugging complex hardware, firmware and system-level issues  * Experience performing silicon characterization and analysing validation results  * Strong analytical, diagnostic and problem-solving skills  * Excellent communication and collaboration skills with the ability to work effectively across multidisciplinary teams  Desirable * Experience with memory IP bring-up environments, firmware or validation software  * Experience with DDR or HBM PHY behaviour, memory controller architectures, training algorithms and calibration flows  * Knowledge of memory subsystem performance analysis and workload characterization  * Experience with memory margining, stress testing and reliability validation  * Familiarity with JTAG, trace infrastructure and low-level debug tools  * Experience with high-performance compute, AI accelerator or data center systems  * Understanding of signal integrity and power integrity considerations in high-speed memory systems  * Experience developing validation automation frameworks and regression environments  * Experience supporting first-silicon bring-up and production readiness activities