MEET ARAGO AND THE ARAGONIANS

Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating

breakthroughs at the intersection of AI and semiconductors.

Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine

learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs.

Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast

achievements. Our work is guided by these core principles:

1. Do great things: we deliver work we’re proud to sign our name to.

2. High velocity: speed matters. We move quickly, one step at a time.

3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie.

Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech

venture firms and exited founders.

WHAT YOU’LL DO

Play a critical role in ensuring the functional integrity, performance, and reliability of next-generation optical chips.

REQUIRED SKILLS AND EXPERIENCE

Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.

Proven fluency and hands-on expertise in SystemVerilog for verification.

Demonstrated prior experience with the UVM framework and modern verification environments.

Direct knowledge of standard protocols (AXI/AXIStream, APB/AHB, I2C, JTAG, PCIe) and experience verifying digital logic for

high-speed interfaces.

Practical experience verifying RISC-V CPU designs or equivalent digital processor architectures within an ASIC context.

Strong analytical and communication skills for customer-driven projects and interdisciplinary teamwork.

Language: English at a proficient level. French is a plus.

RESPONSIBILITIES

Develop robust verification plans for complex digital and mixed-signal optical chip designs.

Collaborate closely with architects, designers, and customers to understand logic requirements, translate them into

verification strategies, and deliver clear, actionable feedback throughout the development process.

Perform netlist-level simulations with SDF back-annotation for timing-accurate verification

Support FPGA/ASIC bring-up and post-silicon validation as needed

Develop, maintain, and optimize testbenches and verification components using advanced SystemVerilog features, such as

constrained random testing, assertions, and transaction-level modeling, to create robust coverage-driven environments.

Design scalable, reusable UVM-based environments and components (e.g., agents, monitors, scoreboards) for block- and

system-level verification. Employ UVM to achieve regression automation, functional coverage closure, and high bug-detection

efficiency.

Develop and execute verification strategies for digital blocks implementing or interfacing with PCI Express (PCIe). Apply

protocol-checking, compliance validation, error injection, and debug skills for PCIe endpoints and root complex devices. Use

protocol analyzers and simulation environments to validate correct implementation across all protocol layers.

Participate in the verification of RISC-V CPU cores and subsystems. Create test plans targeting processor modules (ALU,

decoder, register file, control logic), with reference model comparisons, signature checks, and coverage of edge-case

scenarios. Leverage formal verification and compliance suites for thorough design validation.

Plan and perform end-to-end ASIC verification, from block-level testbenches to full-chip integration. Execute functional and

regression tests, formal verification, and coverage analysis. Debug and resolve design issues, ensuring pre-silicon reliability

before manufacturing. Engage in design reviews and system-level protocol validation with cross-functional teams.

DESIRED ATTRIBUTES

Proactive in anticipating and mitigating design risks, including the assessment of undetected flaws via coverage-driven and

formal verification.

Proven ability to deliver in fast-paced, collaborative startup environments.

Ownership mindset, attention to detail, and commitment to high product quality.

PAY AND BENEFITS

Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar

positions.

Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers).

Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location.

Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days

of PTO, in addition to public holidays.

Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and

individual drive.

Reimbursement of 50% of the public transport subscription fee.

A high-paced, multicultural (with 10 nationalities), and engineering-led environment.

OUR HIRING PROCESS: YOUR JOURNEY TO ARAGO

Screening Call : Get to know you beyond your CV.

Technical meeting : Deep dive into your past projects and technical achievements.

CEO Interview : Assess the fit with the team’s culture and long-term vision.

Reference Calls: Mandatory calls with your former managers to validate strengths, weaknesses, and work style.

Technical Assessment: Take-home technical assignment crafted to the role you’re applying for.

Final Interview : Discuss your technical assignment and address any remaining questions with team members.

Role

Digital Verification Engineer

Locations

Paris Offices

Published

July 25

Deadline

August 16

Tags for this job

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