Senior Hardware Design Engineer

Arago

MEET ARAGO AND THE ARAGONIANS Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors. Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs. Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles: 1. Do great things: we deliver work we’re proud to sign our name to. 2. High velocity: speed matters. We move quickly, one step at a time. 3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie. Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders. WHAT YOU’LL DO Design high-performance analog and RF ICs optimized for precision, power, and area, driving Arago’s prototype and product iterations from architecture to silicon validation. RESPONSIBILITIES * Design and simulate analog and RF integrated circuits, including critical blocks such as amplifiers, mixers, PLLs, ADCs, DACs, and bias/reference circuits, with a focus on signal integrity, linearity, and precision. * Optimize circuits for power, area, and performance trade-offs, ensuring designs meet system-level requirements across process, voltage, and temperature (PVT) variations. * Collaborate closely with optics, simulation and PCB teams to define architecture and block-level specifications for Arago’s successive prototypes and product iterations, ensuring tight alignment with overall performance and integration goals. * Work with layout engineers to guide floor-planning and physical design, minimizing parasitic effects and preserving analog precision in layout-sensitive blocks. * Support post-silicon validation and bring-up, defining test plans, analyzing lab measurements, and correlating results with simulation to refine future design iterations. * Language: English at a proficient level. French is a plus. REQUIRED SKILLS AND EXPERIENCE * A sound mathematical understanding and deep physical intuition of analog electronics, as well as analog voltage-to-current and current-to-voltage conversion at low and high frequencies. * Experience in designing high-precision analog systems for signal processing or power electronics. Experience working with high-frequency analog signals is valued. * Extensive experience in IC design and post-layout design methodology using standard industry tools like Cadence Virtuoso. * Proficiency in designing and optimizing mixed-signal circuits, including DACs and ADCs at low (kHz-MHz) and high (>GHz) frequencies, and signal conditioning circuits, ensuring flawless integration between analog RF components and digital processors. * Strong understanding of signal integrity, crosstalk, and noise reduction techniques in mixed-signal environments, particularly in high-frequency RF systems interfacing with digital processors. * Advanced node experience required (<28nm). PAY AND BENEFITS * Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions. * Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers). * Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location. * Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays. * Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive. * Reimbursement of 50% of the public transport subscription fee. * A high-paced, multicultural (with 9 nationalities), and engineering-led environment.

Arago

MEET ARAGO AND THE ARAGONIANS Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors. Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs. Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles: 1. Do great things: we deliver work we’re proud to sign our name to. 2. High velocity: speed matters. We move quickly, one step at a time. 3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie. Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders. WHAT YOU’LL DO As a Senior Signal Processing Engineer, you sit at the intersection of our physical and digital layers, translating hardware reality into mathematical clarity. You will work hands-on with the optics, analog, and digital teams to co-optimize the design of our compute engine. You're a strong fit if C/C++ is your primary tool and your background spans environments such as telecom, high-speed sensing, optimal control, signal processing, or related fields. REQUIRED SKILLS AND EXPERIENCE * Experience: Minimum 5 years of experience in relevant industries (telecom, high-speed sensors, optimal control, signal processing, or related fields). * Programming: Extensive experience in C/C++ and Python. * Education: Major in Mathematics, Physics, or Informatics with deep expertise in numerical analysis, optimization, and mathematical modeling. * Systems Modeling: Strong ability to identify and model dominant sources of variability, noise, and distortion using both analytical tools and numerical simulations. * Problem Solving: A high level of curiosity and a "first principles" approach to solving non-standard problems in hardware-software co-design. * Language: English at a proficient level. French is a plus. RESPONSIBILITIES * Collaborate with optics, analog, and digital teams to deduce how low-level hardware decisions affect final chip characteristics and AI model performance. * Design and build proprietary internal tools for faithful simulations and hardware optimization. * Analyze the impact of physical noise and signal distortion on system performance, creating mathematical frameworks to mitigate these effects. * Develop models that predict the behavior of light-matter interaction within our architecture to guide the digital and analog design teams. * Drive the mathematical validation of our architecture, ensuring that every design choice is backed by rigorous numerical proof. PAY AND BENEFITS * Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions. * Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers). * Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location. * Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays. * Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive. * Reimbursement of 50% of the public transport subscription fee. * A high-paced, multicultural (with 10 nationalities), and engineering-led environment. OUR HIRING PROCESS: YOUR JOURNEY TO ARAGO * Screening Call : Get to know you beyond your CV. * Technical meeting : Deep dive into your past projects and technical achievements. * CEO Interview : Assess the fit with the team’s culture and long-term vision. * Reference Calls: Mandatory calls with your former managers to validate strengths, weaknesses, and work style. * Technical Assessment: Take-home technical assignment crafted to the role you’re applying for. * Final Interview : Discuss your technical assignment and address any remaining questions with team members.

Arago

MEET ARAGO AND THE ARAGONIANS Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors. Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs. Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles: 1. Do great things: we deliver work we’re proud to sign our name to. 2. High velocity: speed matters. We move quickly, one step at a time. 3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie. Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders. WHAT YOU’LL DO As a Senior Packaging Engineer, you will lead IC packaging initiatives from conceptualization and design to manufacturing process selection. You will establish the necessary supply chain, manage sub-contractors, and oversee the NPI and ramp-up phases for current and future Arago devices. REQUIRED SKILLS AND EXPERIENCE * Master's degree in Electrical Engineering or Integrated Circuits Design. * 5+ years of experience in the semiconductor and photonic packaging industry. * Proficiency in heterogeneous integration and packaging processes, including wafer dicing (stealth, blade, diamond scribing), high-density Cu pillars and advanced bumping, flip-chip, redistribution layer and encapsulation (thermal lid, compression molding, glob-top), die attach and bonding techniques (epoxy, attach film, reflow, thermocompression, eutectic, laser-assisted bonding, Cu-Cu direct bonding), wirebonding, and 2.5D/3D integration schemes (back grinding, TSV reveal, die stacking, interposer). * Strong expertise in photonic and optoelectronic packaging and micro-scale optical alignment, including passive and active alignment of lenses and optical fibers, fine die placement (precision < 1µm), and experience with InP, GaAs, and other non-Si semiconductors. * Proficiency in thermal, mechanical, and EM simulations. * Experience with Cadence Allegro Package Designer, Altium, Cadence Virtuoso, Cadence Sigrity, ANSYS Mechanical, HFSS, and SIwave. * Strong understanding of packaging industrialization, production flows, high-yield and scale manufacturing, failure analysis, and Six Sigma methodology is a plus. * Language: English at a proficient level. French is a plus. RESPONSIBILITIES * Design packaging solutions spanning from initial drawings and simulations to DFM. * Identify, vet, and manage external sub-contractors. * Collaborate cross-functionally with IC design, optical, and PCB teams to align packaging specifications across domains. * Lead the chip industrialization process, ensuring high yield and Cpk. * Conduct thorough failure analysis and debugging. PAY AND BENEFITS * Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions. * Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers). * Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location. * Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays. * Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive. * Reimbursement of 50% of the public transport subscription fee. * A high-paced, multicultural (with 10 nationalities), and engineering-led environment.