Senior Debug Validation Engineer

Graphcore

ABOUT US Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. JOB SUMMARY Reporting to senior leadership within Architecture and Validation, the Debug Validation Lead will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness. This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. THE TEAM The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems. The team works across the full product lifecycle, supporting first silicon bring-up, subsystem validation, system integration and production readiness activities. Engineers collaborate closely with hardware, firmware, software and systems teams to investigate complex failures, develop debug methodologies and improve validation infrastructure. RESPONSIBILITIES AND DUTIES * Lead post-silicon debug and validation activities for AI compute silicon and platform technologies * Contribute to debug and validation activities across multiple projects and milestones * Drive prioritisation, planning and execution of debug and validation activities across multiple projects and milestones * Investigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validation * Develop structured debug methodologies and failure analysis processes to improve issue resolution efficiency * Collaborate closely with architecture, RTL, firmware, software and systems engineering teams to identify root causes and implement corrective actions * Drive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditions * Develop and enhance automated debug, regression and validation infrastructure using Python and related technologies * Analyse logs, traces, telemetry and hardware data to isolate and characterize system failures and performance issues * Support development of validation tests, debug tooling and custom diagnostics to improve coverage and observability * Define validation metrics, debug workflows and reporting standards to ensure consistent and repeatable analysis * Drive continuous improvement of debug processes, validation methodologies and engineering workflows * Communicate technical risks, status and recommendations clearly to engineering leadership and cross-functional stakeholders * Support silicon readiness reviews and contribute to product quality and release decisions * Contribute to continuous improvement of debug methodologies, validation infrastructure and engineering workflows CANDIDATE PROFILE ESSENTIAL: * Strong experience in bare metal environments * Good knowledge of SoC and platform architectures * Expertise in debug infrastructure and post-silicon debug methodologies * Strong programming skills in Python, C, or debug scripting languages such as CMM * Highly motivated self-starter with a collaborative and team-oriented approach * Ability to work across teams and programming languages to identify root causes of deep and complex issues * Experience of the post-silicon validation process applied in digital ASIC environments * Strong Linux and Python experience * Exceptional communication skills and the ability to collaborate effectively to solve complex problems * Excellent problem-solving, analytical and diagnostic skills * Deep knowledge of scan, DFT, JTAG and trace infrastructure * Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies and system-level debug techniques * Ability to work independently on technically complex debug and validation activities across hardware, firmware and software domains DESIRABLE * Understanding of DFT flows from insertion through post-silicon validation * Experience developing tooling for parsing and analysing debug data, including scan dump parsing * Driver-level experience with one or more of the following technologies: * PCIe * Ethernet * Memory technologies including LPDDR, DDR and HBM * Peripheral interfaces such as I2C, I3C and SPI * Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB and STM * Good knowledge of mixed-signal building blocks such as PLLs, high-speed PHYs and IC control/communication protocols * Experience with Arm CPU architectures, system IP and associated debug tooling * Experience with AMBA protocols * Understanding of ML applications and associated workloads * Experience in characterization, failure analysis, test development, statistical analysis and customer support

Graphcore

Job Summary Reporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms. The role will focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams to ensure robust memory subsystem functionality, performance and reliability. The successful candidate will take ownership of significant validation activities, contribute to debug and root-cause analysis efforts, and help improve validation methodologies, automation and infrastructure. The Team The Memory Validation team sits within the Validation organisation and is responsible for the bring-up, validation, characterization and debug of memory subsystems across Graphcore silicon and platform products. The team supports DDR and HBM validation activities throughout the product lifecycle, from first silicon through production readiness. Engineers work closely with architecture, RTL, firmware, characterization, systems and platform teams to ensure memory technologies meet functionality, performance, reliability and performance objectives. Responsibilities and Duties * Execute validation and bring-up activities for DDR and HBM memory subsystems  * Verify memory bring-up software, firmware and scripts against defined project requirements  * Debug firmware, hardware and system-level issues and contribute to root-cause analysis activities  * Analyse system logs, validation data and characterization results to identify failures and performance issues  * Perform PHY characterization and analog-level analysis during stress testing and validation activities  * Develop and execute functional, stress, performance and corner-case validation tests  * Perform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation  * Characterize memory bandwidth, latency, training behaviour and subsystem stability across operating conditions  * Develop Python-based automation, test infrastructure and reporting tools to improve validation efficiency  * Collaborate with architecture, RTL, firmware and platform teams to investigate and resolve technical issues  * Contribute to memory subsystem debug activities spanning silicon, firmware, board and system domains  * Support development of validation methodologies, debug procedures and reporting frameworks  * Contribute to continuous improvement of validation infrastructure and engineering processes  * Support silicon characterization, production readiness and qualification activities  * Document validation results and communicate findings to the wider engineering team  Candidate Profile Essential * Strong experience validating DDR, LPDDR, HBM or related DRAM technologies  * Deep understanding of DRAM architecture, memory subsystem operation and memory controller functionality  * Experience with firmware, BIOS and Embedded C development  * Strong programming skills in C and Python  * Hands-on experience using laboratory equipment including oscilloscopes and related measurement instrumentation  * Experience interfacing with low-speed peripherals including GPIO, SPI, I2C and UART/serial interfaces  * Experience performing functional testing and signal measurements including voltage, frequency and timing analysis  * Strong knowledge of embedded systems and microcontroller-based platforms  * Hands-on experience with board bring-up and hardware validation activities  * Experience debugging complex hardware, firmware and system-level issues  * Experience performing silicon characterization and analysing validation results  * Strong analytical, diagnostic and problem-solving skills  * Excellent communication and collaboration skills with the ability to work effectively across multidisciplinary teams  Desirable * Experience with memory IP bring-up environments, firmware or validation software  * Experience with DDR or HBM PHY behaviour, memory controller architectures, training algorithms and calibration flows  * Knowledge of memory subsystem performance analysis and workload characterization  * Experience with memory margining, stress testing and reliability validation  * Familiarity with JTAG, trace infrastructure and low-level debug tools  * Experience with high-performance compute, AI accelerator or data center systems  * Understanding of signal integrity and power integrity considerations in high-speed memory systems  * Experience developing validation automation frameworks and regression environments  * Experience supporting first-silicon bring-up and production readiness activities

Graphcore

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role combines deep technical expertise with people leadership responsibilities, including team development, prioritisation, mentoring and delivery coordination across multiple projects and stakeholders. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debug complex issues, optimize workloads and continuously improve validation infrastructure and methodologies. Responsibilities and Duties * Define and lead validation strategies for power, thermal and performance characterization of AI compute silicon and platforms * Lead, mentor and support a team of validation engineers, providing technical guidance, coaching and career development * Drive planning, prioritisation and execution of validation activities across multiple projects and milestones * Develop comprehensive validation plans covering functional, stress, workload and corner-case scenarios * Lead post-silicon bring-up and characterization activities for power and performance validation * Drive validation of CPU, memory, interconnect and high-speed I/O subsystems under complex workload conditions * Develop scalable automation frameworks, regression infrastructure and reporting tools using Python * Design and execute benchmark workloads, parameter sweeps and performance experiments to identify optimization opportunities * Collaborate with architecture, RTL, firmware, software and systems teams to debug and resolve complex technical issues * Define validation metrics, pass/fail criteria and reporting methodologies to ensure repeatable and high-quality analysis * Guide development of custom workload generators and micro-benchmarks where required * Analyse power, thermal and performance data to identify bottlenecks and recommend improvements * Contribute to continuous improvement of validation processes, tooling and engineering practices * Communicate technical findings, project status, risks and recommendations clearly to stakeholders and engineering leadership * Support hiring activities, onboarding and team growth initiatives Candidate Profile Essential: * Strong experience in power and performance validation, silicon characterization or system performance engineering * Experience leading or managing engineering teams within a technical environment * Deep understanding of modern SoC architecture, including CPU, memory, interconnect and high-speed I/O technologies * Strong Linux systems knowledge and low-level performance analysis experience * Strong Python programming skills for automation, orchestration and data analysis * Experience with benchmarking and profiling tools such as stress-ng, fio, perf, iperf or equivalent technologies * Experience debugging complex hardware and software interactions * Ability to define structured validation methodologies, workload models and test strategies * Strong analytical skills with the ability to interpret large datasets and identify system bottlenecks * Strong communication, stakeholder management and cross-functional collaboration skills * Ability to lead complex technical initiatives across geographically distributed teams Desirable * Experience with AI accelerator, GPU or high-performance compute architectures * Experience with pre-silicon modelling or simulation environments * Knowledge of power management technologies and silicon characterization methodologies * Programming experience in C/C++ for low-level system or benchmark development * Familiarity with hardware instrumentation and telemetry systems * Experience working with high core-count or large-scale compute systems * Experience scaling or building technical engineering teams