Senior/Staff Engineer - Computing Architecture

Axelera AI

About Us Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years, we have raised a total of $370 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 18 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands. We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million. Our unwavering commitment to innovation has firmly established us as a global industry pioneer. Are you up for the challenge? Position Overview As a Senior or Staff Logical Design Engineer, you will join a team responsible for the micro-architecture, implementation and execution of in-house designed AI products. Your role will be critical in achieving the highest level of quality and performance as well as ensuring continued innovation in both design and design flow. This is an opportunity to work with cutting-edge technology and a dedicated team of professionals who share your passion for pushing the boundaries of what's possible. Key responsibilities: * Collaborate with cross-functional teams to clarify and comprehend intricate design specifications and requirements. * Architect and implement advanced micro-architectures from high-level specifications for silicon components, adhering to performance, power, and area (PPA) metrics. * Employ industry-standard design tools and methodologies to fashion and optimize digital logic circuits. * Conduct block and system-level RTL coding, ensuring optimal performance, power, and area (PPA) metrics. * Integrate various IPs/Sub IPs into the top-level SoC. * Perform static checks (lint, cdc, equivalence checks) to enhance the quality of the RTL. * Automate tasks using scripting for efficiency gains. * Undertake comprehensive functional verification and collaborate closely with verification engineers to ensure the correctness of the design. * Actively engage in design reviews, contributing technical expertise to enhance overall design quality. * Work collaboratively with physical design engineers to address design-for-manufacturability (DFM) and design-for-test (DFT) considerations. Qualifications / skills Education: A degree in electronics engineering, electrical engineering or computer science or other relevant discipline. Experience: A minimum of 5 years of experience and proven expertise in silicon logical design, with a successful track record in RTL coding and synthesis, digital design, SoC, and integration of 3rd-party IPs (PCIe, LPDDR), with fluency in Verilog. Expertise: Mastery of industry-standard Electronic Design Automation (EDA) tools for design and verification. Deep understanding of intricate digital design principles, covering clock domain crossing, low-power design, and timing closure. Scripting: Proficiency in scripting languages such as Python, shell or Tcl for automation. Collaboration / Team Player: Demonstrated ability to work closely with architecture, verification, physical design and software teams to ensure comprehensive verification coverage. Problem Solving: Strong analytical and problem-solving skills. Communication: Excellent written and verbal communication skills in English. Comfortable working with a team spread across 15 countries. Location We offer a flexible working arrangement, with options to: * Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom) if you're already based in the vicinity. * Work fully remotely from any European country (incl. the UK) you are already in. * Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven). What we offer  This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.    An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team.  At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.

Axelera AI

About Us Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years, we have raised a total of $370 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 18 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands. We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million. Our unwavering commitment to innovation has firmly established us as a global industry pioneer. Are you up for the challenge? Position Overview As a Senior Advanced Packaging & Power Delivery Engineer at Axelera AI, you will play a pivotal role in shaping the silicon and packaging architecture of our next-generation AI accelerators. You will own power-delivery design across the full stack - from on-die power grids to package and PCB PDN - and bring deep expertise in advanced packaging technologies to help us scale from today's products to tomorrow's multi-chiplet, 3D-integrated systems. Working within our R&D Custom Design team and collaborating closely with Silicon Engineering and AI Integrated Systems, you will be at the intersection of analog design, packaging innovation, and product delivery - with real ownership and direct impact on the chips we ship. Key responsibilities: * Own power-delivery design end to end, from on-die power grids to package and PCB PDN design and analysis. * Lead advanced packaging architecture decisions for 2.5D/3D stacking, multi-chiplet integration, and interposer/substrate co-design. * Perform SI/PI verification and sign-off across the full stack, ensuring power integrity and signal integrity targets are met. * Collaborate with the AIIS and Silicon Engineering teams to align power delivery and packaging solutions with product and silicon requirements. * Support thermal and integration reviews for current and future products * Develop and maintain power-delivery methodology, flows, and design guidelines within the Custom Design toolchain. * Identify and mitigate single-point-of-failure risks in SI/PI workstreams; mentor and grow the team's packaging expertise. * Engage with external partners, substrate/interposer vendors, and OSAT houses to co-develop advanced packaging solutions.   Qualifications: Required * Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field; PhD is a plus. * 7+ years of experience in power delivery and/or advanced packaging design in a semiconductor or deep-tech environment. * Demonstrated expertise in on-die power grid design and package/PCB PDN analysis. * Hands-on experience with 2.5D and/or 3D IC packaging technologies, multi-chiplet integration, and interposer/substrate co-design. * Proficiency with industry-standard EDA tools for power integrity, PDN simulation, and package design. * Ability to work cross-functionally and communicate complex technical trade-offs to diverse stakeholder groups. * Strong written and spoken English communication skills.   Nice to Have * Experience with SI/PI verification and sign-off methodologies. * Familiarity with thermal modeling and co-simulation for integrated packages. * Exposure to AI accelerator or custom ASIC design flows. * Experience collaborating with OSAT partners, substrate vendors, or research institutes (e.g., imec). * Knowledge of advanced node custom and analog design practices. Location We offer a flexible working arrangement, with options to: * Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom) if you're already based in the vicinity. * Work fully remotely from any European country (incl. the UK) you are already in. * Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven). Kindly note that priority will be given to candidates who are [interested in being] based in Belgium or Italy. What we offer  This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.    An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team.  At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.

Axelera AI

About Us Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years, we have raised a total of $370 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 18 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands. We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million. Our unwavering commitment to innovation has firmly established us as a global industry pioneer. Are you up for the challenge? Position Overview We are looking for a Senior Platform Architect to own the platform-level architecture for our datacenter AI accelerator systems — from server through rack integration and, eventually, full datacenter deployment. The role sits within the System Architecture team, and marks our expansion from edge AI into the datacenter. You’ll take compute, memory, and connectivity requirements defined by the broader System Architecture team and translate them into architectural requirements on our hardware platforms. You own how accelerators are composed into systems to execute workloads effectively, defining system topology, host integration, memory organization and platform-level requirements to achieve performance, scalability and operability. The role is primarily in close collaboration with the AI Infrastructure Systems (AIIS) division that builds our board- and system-level products, as well as with the silicon and software divisions. Finally, you will be engaged with strategic customers and ecosystem partners on architecture requirements and technical alignment. Key responsibilities: * Define the platform-level architecture for our datacenter AI accelerator systems, spanning server board design, rack integration, and datacenter-level deployment. * Translate system-level compute, memory, and interconnect requirements — defined in collaboration with the broader System Architecture team and product division — into concrete hardware platform specifications. * Specify physical interconnect infrastructure — defining the architectural requirements and trade-offs that the AI Infrastructure Systems division executes against, including how interconnect characteristics impact system-level workload performance. * Define host, storage and networking integration and organization at the hardware level, covering PCIe and CXL, as well as system-level power budgeting. * Ensure scaled-up and scaled-out designs sustain target performance as systems grow from single nodes to large clusters. * Define operability and RAS (reliability, availability, serviceability) requirements across redundancy architecture, hot-swap capability, telemetry and management interfaces (BMC/IPMI/Redfish), and fault containment to ensure platforms are manageable and dependable in production. * Take a leading technical role in the system architecture team, interfacing directly with key partners and internal stakeholders to align architecture decisions, including the AI Infrastructure Systems division, silicon, product management, software, and customers, system integrators and ecosystem partners on architecture requirements — with commercial engagement and design ownership sitting with the AIIS Director. * Drive methodology and best practices for platform-level design as the team scales. Qualifications: * Experience: Significant experience (5+ years) in system, platform, or hardware architecture, with a strong track record at server and/or rack scale. * Core knowledge: Scale-up and scale-out system design, distributed workload mapping, functional partitioning, and interconnect/fabric architecture. * Fabrics & interconnect: Deep, hands-on understanding of Ethernet, UALink, optical, and switched-fabric technologies, and the ability to reason about their system-level performance trade-offs. * Systems thinking: Ability to connect workload characteristics to hardware architecture and to quantify the impact of design choices on end-to-end performance. * Leadership and collaboration: Demonstrated ability to lead and collaborate across multidisciplinary teams and to interface effectively with partners and senior stakeholders. * Bonus: Experience architecting AI/HPC accelerator systems, familiarity with distributed training/inference workloads, and exposure to data-center-scale deployment. * Strong problem-solving skills, a collaborative mindset, and a passion for building systems at scale. Location We offer a flexible working arrangement, with options to: * Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom) if you're already based in the vicinity. * Work fully remotely from any European country (incl. the UK) you are already in. * Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven). Kindly note that priority will be given to candidates who are [interested in being] based in Belgium or Italy. What we offer  This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.    An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team.  At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.