Search results for "RTL Debugging"

Company description: Ericsson AB Job description: Join our Team About This Opportunity Join our innovative team to use your expertise and elevate your ASIC verification to the next level within Ericsson. We specialize in the top-level verification of cutting-edge ASICs that power complex, high-performance systems. Integrated multi-chip-modules are replacing monolithic solutions. Our designs hold several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe. As an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security.   You will play an important role in the team developing software driven tests run in CI regressions on our four platforms, SystemC/TLM simulation, RTL simulation, hardware emulation, and eventually on Silicon.   What You Will Do Bring ASIC designs into hardware emulators for pre-silicon verification and prepare tests for ASIC silicon prototype bring-ups Drive development of hybrid environments where the ASIC is split between an emulator and TLM/SystemC Develop transactors for hybrid environments Manage emulation regressions and support teams in resolving testcase issues Maintain and update existing emulator platforms Define strategies and collaborate across teams using hardware emulators Contribute to software-driven test development written in C, with debugging via EDA simulation tools, SW debuggers, and hybrid environments   The Skills You Bring Essential: Experience building hardware emulation environments using Siemens Veloce, Cadence Palladium, or Synopsys Zebu Solid RTL debugging skills in SystemVerilog or VHDL C programming skills for ASICs or embedded software Desired: HW/SW co-debugging using SW debuggers for C-code on multi-core ASIC designs Debugging experience on HW emulators and/or Silicon Experience simulating and debugging on SystemC/TLM platforms Education: Master's degree in Computer Engineering, Electrical Engineering, or related field

Description- Professional Experience * 8–15+ years of experience in ASIC/SoC design and development. * Demonstrated ownership of multiple ASIC projects from specification to tape-out and bring-up. * Proven leadership in defining and delivering system and chip architectures. Technical Expertise RTL & Microarchitecture * Expert-level proficiency in Verilog/SystemVerilog for RTL design. * Solid experience developing microarchitecture specifications for complex subsystems. * Familiarity with clocking, resets, power domains, FSMs, pipelining, and parallelism. Verification & Simulation * Good understanding of functional verification methodologies (SystemVerilog, UVM). * Ability to collaborate with verification teams on test plans, assertions, and coverage. * Familiar with simulators (e.g., VCS, Questa, ModelSim). Synthesis & Static Timing Analysis * Hands-on experience with logic synthesis tools (Synopsys Design Compiler, Cadence Genus). * Skilled in timing constraint definition (SDC) and timing closure using PrimeTime. * Able to guide physical design teams on floorplanning, congestion, and timing paths. Architectural Design & System Integration * Ability to define and document chip-level architecture, including: * Block diagrams, interface protocols (AXI, PCIe, Ethernet, etc.). * Data and control flow, memory hierarchies, and DMA engines. * Power, performance, area (PPA) trade-off analysis. * Skilled in specification development: architectural specs, ICDs, design guides. Low Power & DFT * Knowledge of UPF/CPF, clock gating, power domains, DVFS. * Familiar with DFT techniques: scan chains, MBIST, boundary scan (useful for collaboration with DFT teams). Modeling & High-Level Design * Experience with performance modeling using Python, C/C++, SystemC. * Capability to run system-level simulations and evaluate architectural choices. * (Optional) Familiarity with High-Level Synthesis (HLS) flows. Scripting & Automation * Proficiency in Python, Perl, or Tcl for design and flow automation. Soft Skills & Leadership * Strong debugging and problem-solving skills across RTL, synthesis, and system levels. * Capable of leading cross-functional teams including design, verification, physical design, firmware, and software. * Experience mentoring junior engineers and reviewing their designs. * Excellent verbal and written communication for documenting specs and collaborating with stakeholders. Bonus Qualifications * Knowledge of AI/ML accelerators, networking, or video processing pipelines. * Experience with multi-die (chiplet) integration, 2.5D/3D packaging. * Understanding of security architectures, encryption modules, or hardware IP protection. * Background in post-silicon validation, lab bring-up, or FPGA prototyping. * Exposure to embedded firmware/software, drivers, or hardware-software co-design. We are primarily looking for someone who can work on-site in Stockholm in accordance with the client’s office policy, which requires a minimum of three days per week at the office. Candidates who can only work remotely are also welcome to apply, but they will not be prioritized initially. Start date 2026-02-06 End date 2026-12-31 Submission Deadline-2026-02-02