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Your commute settings are active, but since Skåne is outside your commuting range, we are showing all 5 open positions matching keyword "SystemVerilog" in the region, sorted by compatibility score (best commute and salary first). All of these listings are active and open for applications.
The most recent job was posted by LUNDS UNIVERSITET for the role of Postdoktor till forskargruppen för systemvirologi.
🛡️ 38% soliditet
Malmö•Heltid•Posted: Jun 29•Deadline: Aug 17
PostdoktorSystemvirologiBioinformatikBiostatistikTranslationell medicinForskningsmetodik
Lunds universitet grundades 1666 och rankas återkommande som ett av världens främsta lärosäten. Här finns omkring 46 000 studenter och 8 500 medarbetare i Lund, Helsingborg och Malmö. Vi förenas i vår strävan att förstå,...Show more
🛡️ 37% soliditet
Göteborg•Heltid•Posted: Jun 28•Deadline: Jul 9
SystemVerilogRTL DesignTiming ClosureSenior ASIC/FPGA Engineer
Help build the hardware core of a technology that makes computing faster, leaner, and more energy-efficient - at scale. The role You'll own complex RTL development end-to-end, from architectural trade-offs and early expl...Show more
🛡️ 61% soliditet
Lund•Heltid•Posted: Jun 11•Deadline: Jul 10
ASIC VerificationHardware EngineeringSystem-on-ChipVerification EngineerIP VerificationObject-Oriented Programming
Do you want to work with the core of a global tech company's business? How would it feel to be in a team that verifies that one thing our product portfolio depends on? With us in the ASIC verification team, you will be a...Show more
🛡️ 27% soliditet
Lund•Heltid•Posted: May 16•Deadline: Aug 14
ASIC DesignerSystemVerilogFPGAUVMTelecomIntegration
We are currently looking for an ASIC designer. You will be involved in new and existing ASIC projects working in teams. We are looking for two different roles: 1 ASIC designer 1 ASIC designer working also with integratio...Show more
🛡️ 27% soliditet
Lund•Heltid•Posted: Apr 17•Deadline: Jul 17
ASIC/FPGA VerificationSystemVerilogUVMVHDLEmulationHardware Engineering
Scope: Verification planning, specification, and Verification environment (creation / adaptation / maintenance) Test case creation & execution Requirements: Experience in FPGA/ASIC Top-Level Verification Excellent skills...Show more
Commute
Commute Limit45 min
🚀 15 min🇸🇪 45 min avg🚌 90 min
Commute Map (Skåne)
Optimal (< 25 min)
Standard (25-50 min)
Long commute (> 50 min)
Outside limit (> 45 min)