Senior System Software Engineer - Bengaluru, multiple vacancies

Coupang

Company Introduction   We exist to wow our customers. We know we’re doing the right thing when we hear our customers say, “How did I ever live without Coupang?” Born out of an obsession to make shopping, eating, and living easier than ever, we’re collectively disrupting the multi-billion-dollar e-commerce industry from the ground up. We are one of the fastest-growing e-commerce companies that established an unparalleled reputation for being a dominant and reliable force in South Korean commerce.    We are proud to have the best of both worlds — a startup culture with the resources of a large global public company. This fuels us to continue our growth and launch new services at the speed we have been since our inception. We are all entrepreneurs surrounded by opportunities to drive new initiatives and innovations. At our core, we are bold and ambitious people that like to get our hands dirty and make a hands-on impact. At Coupang, you will see yourself, your colleagues, your team, and the company grow every day.   Our mission to build the future of commerce is real. We push the boundaries of what’s possible to solve problems and break traditional trade-offs. Join Coupang now to create an epic experience in this always-on, high-tech, and hyper-connected world.     Role Overview We are seeking a Sr Staff System Engineer, GPU Fleet for our Coupang Intelligent Cloud (CIC) team,  to serve as the senior technical owner for our hyperscale GPU compute infrastructure. In this role, you will define fleet architecture, drive reliability and automation at scale, and lead the operation and evolution of GPU systems supporting large‑scale AI training and inference workloads. This is a hands‑on, staff‑level individual contributor role with broad technical ownership, high operational impact, and significant cross‑functional influence across hardware, infrastructure, and datacenter operations. CIC builds the infrastructure for abundant intelligence. We partner with leading AI labs, governments, and enterprises to deliver hyperscale GPU compute with high reliability, performance, and efficiency. Our infrastructure supports some of the most demanding AI training and inference workloads in production today. We operate with urgency, deep ownership, and a strong bias toward execution. Reliability, operational excellence, and rigorous systems engineering are core to our business.   What You Will Do As a Sr Staff System Engineer, GPU Fleet, you will be the senior technical owner for CIC’s large‑scale GPU compute infrastructure. This is a hands‑on senior individual contributor role with fleet‑level responsibility and broad cross‑functional influence. You will define the technical direction for how GPU fleets are architected, operated, automated, and evolved across multiple generations of hardware. Your work will directly affect fleet reliability, operating efficiency, scalability, and customer success. This role does not involve people management, but it carries principal‑level scope, autonomy, and decision‑making authority across infrastructure, hardware, and operations.   Key Responsibilities: Fleet Architecture & Technical Ownership * Own the end‑to‑end technical architecture of hyperscale GPU fleets, including hardware platform selection, firmware strategy, OS configuration, drivers, networking, and observability. * Define and enforce technical standards and best practices for fleet reliability, availability, performance, and operability. * Lead major fleet‑wide initiatives such as new GPU platform bring‑ups, multi‑generation hardware transitions, and architectural redesigns. * Evaluate trade‑offs across cost, performance, reliability, and time‑to‑deploy, and make technically sound decisions under ambiguity. Reliability, Availability & Performance * Set and drive fleet‑level reliability, availability, and performance objectives. * Lead root‑cause analysis and resolution of complex, systemic failures affecting large portions of the fleet or multiple datacenters. * Identify recurring failure patterns and drive long‑term fixes spanning hardware, software, automation, and operational processes. * Work directly with hardware vendors and partners to resolve platform‑level issues and influence future hardware designs. Automation & Systems Engineering * Design and build large‑scale automation systems for: * GPU fleet provisioning and lifecycle management * GPU health validation, diagnostics, and certification * Automated remediation, recovery, and replacement workflows * Eliminate manual operational toil through durable, well‑designed tooling that scales with fleet growth. * Ensure all fleet systems are observable, testable, and resilient under failure conditions. Operational Leadership * Act as a senior escalation point for critical production incidents impacting GPU availability or customer workloads. * Participate in on‑call rotations with a strong emphasis on preventing future incidents, not just responding to them. * Lead high‑severity post‑incident reviews and ensure learnings are translated into concrete engineering and process improvements. Technical Influence & Mentorship * Provide technical mentorship and guidance to system and infrastructure engineers across the organization. * Serve as a trusted technical partner to platform engineering, networking, datacenter operations, and leadership teams. * Influence CIC’s long‑term infrastructure roadmap through strong technical judgment and data‑driven recommendations.      Basic Qualifications  * 12+ Years of overall experience with at least 8+ years of experience in Linux systems engineering, infrastructure engineering, or datacenter operations, operating production environments with strict uptime and performance requirements. * Deep, hands‑on expertise in Linux system internals, including process scheduling, memory management, filesystem behavior, networking, kernel behavior, and system performance analysis. * Demonstrated experience operating hardware‑intensive infrastructure in production, including bare‑metal servers at scale. * Proven ability to debug complex issues across multiple system layers, including hardware components, firmware/BIOS, kernel drivers, OS configuration, and user‑space services. * Extensive experience writing production‑grade automation using Python and Bash for provisioning, configuration management, diagnostics, remediation, and fleet operations. * Strong understanding of how to design systems that are observable, resilient, and safe under failure, rather than reliant on manual intervention.   Preferred Qualifications * Direct experience operating large‑scale GPU fleets supporting AI/ML training and/or inference workloads in production. * Familiarity with modern GPU platforms and ecosystems, including GPU drivers, CUDA, NCCL, and high‑performance compute workloads. * Experience with high‑speed interconnects and datacenter networking, such as NVLink, InfiniBand, RDMA, and high‑throughput Ethernet. * Prior ownership of fleet‑wide or platform‑wide initiatives, such as new hardware bring‑ups, major architectural changes, or reliability transformations. * Experience partnering directly with hardware vendors or manufacturers to troubleshoot systemic issues or influence future platform designs. * Strong intuition for failure modes at scale, including cascading failures, correlated faults, and second‑order effects across systems. * History of acting as a technical authority or escalation point for ambiguous, high‑impact production problems. * Ability to mentor engineers through design reviews, technical problem solving, and modelling strong operational ownership. * Experience participating in on‑call rotations and responding to high‑severity production incidents with clear ownership, urgency, and technical leadership. * Strong written and verbal communication skills, including clear post‑incident reviews and technical documentation. Type of work model Hybrid Details to consider  * Those eligible for employment protection (recipients of veteran’s benefits, the disabled, etc.) may receive preferential treatment for employment in accordance with applicable laws.    Privacy Notice   * Your personal information will be collected and managed by Coupang as stated in the Application Privacy Notice located below. https://privacy.coupang.com/en/land/jobs/

Graphcore

ABOUT US Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. JOB SUMMARY Reporting to senior leadership within Architecture and Validation, the Debug Validation Lead will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness. This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. THE TEAM The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems. The team works across the full product lifecycle, supporting first silicon bring-up, subsystem validation, system integration and production readiness activities. Engineers collaborate closely with hardware, firmware, software and systems teams to investigate complex failures, develop debug methodologies and improve validation infrastructure. RESPONSIBILITIES AND DUTIES * Lead post-silicon debug and validation activities for AI compute silicon and platform technologies * Contribute to debug and validation activities across multiple projects and milestones * Drive prioritisation, planning and execution of debug and validation activities across multiple projects and milestones * Investigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validation * Develop structured debug methodologies and failure analysis processes to improve issue resolution efficiency * Collaborate closely with architecture, RTL, firmware, software and systems engineering teams to identify root causes and implement corrective actions * Drive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditions * Develop and enhance automated debug, regression and validation infrastructure using Python and related technologies * Analyse logs, traces, telemetry and hardware data to isolate and characterize system failures and performance issues * Support development of validation tests, debug tooling and custom diagnostics to improve coverage and observability * Define validation metrics, debug workflows and reporting standards to ensure consistent and repeatable analysis * Drive continuous improvement of debug processes, validation methodologies and engineering workflows * Communicate technical risks, status and recommendations clearly to engineering leadership and cross-functional stakeholders * Support silicon readiness reviews and contribute to product quality and release decisions * Contribute to continuous improvement of debug methodologies, validation infrastructure and engineering workflows CANDIDATE PROFILE ESSENTIAL: * Strong experience in bare metal environments * Good knowledge of SoC and platform architectures * Expertise in debug infrastructure and post-silicon debug methodologies * Strong programming skills in Python, C, or debug scripting languages such as CMM * Highly motivated self-starter with a collaborative and team-oriented approach * Ability to work across teams and programming languages to identify root causes of deep and complex issues * Experience of the post-silicon validation process applied in digital ASIC environments * Strong Linux and Python experience * Exceptional communication skills and the ability to collaborate effectively to solve complex problems * Excellent problem-solving, analytical and diagnostic skills * Deep knowledge of scan, DFT, JTAG and trace infrastructure * Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies and system-level debug techniques * Ability to work independently on technically complex debug and validation activities across hardware, firmware and software domains DESIRABLE * Understanding of DFT flows from insertion through post-silicon validation * Experience developing tooling for parsing and analysing debug data, including scan dump parsing * Driver-level experience with one or more of the following technologies: * PCIe * Ethernet * Memory technologies including LPDDR, DDR and HBM * Peripheral interfaces such as I2C, I3C and SPI * Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB and STM * Good knowledge of mixed-signal building blocks such as PLLs, high-speed PHYs and IC control/communication protocols * Experience with Arm CPU architectures, system IP and associated debug tooling * Experience with AMBA protocols * Understanding of ML applications and associated workloads * Experience in characterization, failure analysis, test development, statistical analysis and customer support

Graphcore

ABOUT US Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. JOB SUMMARY Reporting to senior leadership within Architecture and Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness. This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. THE TEAM The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems. The team works across the full product lifecycle, supporting first silicon bring-up, subsystem validation, system integration and production readiness activities. Engineers collaborate closely with hardware, firmware, software and systems teams to investigate complex failures, develop debug methodologies and improve validation infrastructure. RESPONSIBILITIES AND DUTIES * Lead post-silicon debug and validation activities for AI compute silicon and platform technologies * Contribute to debug and validation activities across multiple projects and milestones * Drive prioritisation, planning and execution of debug and validation activities across multiple projects and milestones * Investigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validation * Develop structured debug methodologies and failure analysis processes to improve issue resolution efficiency * Collaborate closely with architecture, RTL, firmware, software and systems engineering teams to identify root causes and implement corrective actions * Drive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditions * Develop and enhance automated debug, regression and validation infrastructure using Python and related technologies * Analyse logs, traces, telemetry and hardware data to isolate and characterize system failures and performance issues * Support development of validation tests, debug tooling and custom diagnostics to improve coverage and observability * Define validation metrics, debug workflows and reporting standards to ensure consistent and repeatable analysis * Drive continuous improvement of debug processes, validation methodologies and engineering workflows * Communicate technical risks, status and recommendations clearly to engineering leadership and cross-functional stakeholders * Support silicon readiness reviews and contribute to product quality and release decisions * Contribute to continuous improvement of debug methodologies, validation infrastructure and engineering workflows CANDIDATE PROFILE ESSENTIAL: * Strong experience in bare metal environments * Good knowledge of SoC and platform architectures * Expertise in debug infrastructure and post-silicon debug methodologies * Strong programming skills in Python, C, or debug scripting languages such as CMM * Highly motivated self-starter with a collaborative and team-oriented approach * Ability to work across teams and programming languages to identify root causes of deep and complex issues * Experience of the post-silicon validation process applied in digital ASIC environments * Strong Linux and Python experience * Exceptional communication skills and the ability to collaborate effectively to solve complex problems * Excellent problem-solving, analytical and diagnostic skills * Deep knowledge of scan, DFT, JTAG and trace infrastructure * Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies and system-level debug techniques * Ability to work independently on technically complex debug and validation activities across hardware, firmware and software domains DESIRABLE * Understanding of DFT flows from insertion through post-silicon validation * Experience developing tooling for parsing and analysing debug data, including scan dump parsing * Driver-level experience with one or more of the following technologies: * PCIe * Ethernet * Memory technologies including LPDDR, DDR and HBM * Peripheral interfaces such as I2C, I3C and SPI * Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB and STM * Good knowledge of mixed-signal building blocks such as PLLs, high-speed PHYs and IC control/communication protocols * Experience with Arm CPU architectures, system IP and associated debug tooling * Experience with AMBA protocols * Understanding of ML applications and associated workloads * Experience in characterization, failure analysis, test development, statistical analysis and customer support