Senior IC Validation Engineer

Graphcore

ABOUT US Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. JOB SUMMARY Reporting to senior leadership within Architecture and Validation, the Debug Validation Lead will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness. This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. THE TEAM The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems. The team works across the full product lifecycle, supporting first silicon bring-up, subsystem validation, system integration and production readiness activities. Engineers collaborate closely with hardware, firmware, software and systems teams to investigate complex failures, develop debug methodologies and improve validation infrastructure. RESPONSIBILITIES AND DUTIES * Lead post-silicon debug and validation activities for AI compute silicon and platform technologies * Contribute to debug and validation activities across multiple projects and milestones * Drive prioritisation, planning and execution of debug and validation activities across multiple projects and milestones * Investigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validation * Develop structured debug methodologies and failure analysis processes to improve issue resolution efficiency * Collaborate closely with architecture, RTL, firmware, software and systems engineering teams to identify root causes and implement corrective actions * Drive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditions * Develop and enhance automated debug, regression and validation infrastructure using Python and related technologies * Analyse logs, traces, telemetry and hardware data to isolate and characterize system failures and performance issues * Support development of validation tests, debug tooling and custom diagnostics to improve coverage and observability * Define validation metrics, debug workflows and reporting standards to ensure consistent and repeatable analysis * Drive continuous improvement of debug processes, validation methodologies and engineering workflows * Communicate technical risks, status and recommendations clearly to engineering leadership and cross-functional stakeholders * Support silicon readiness reviews and contribute to product quality and release decisions * Contribute to continuous improvement of debug methodologies, validation infrastructure and engineering workflows CANDIDATE PROFILE ESSENTIAL: * Strong experience in bare metal environments * Good knowledge of SoC and platform architectures * Expertise in debug infrastructure and post-silicon debug methodologies * Strong programming skills in Python, C, or debug scripting languages such as CMM * Highly motivated self-starter with a collaborative and team-oriented approach * Ability to work across teams and programming languages to identify root causes of deep and complex issues * Experience of the post-silicon validation process applied in digital ASIC environments * Strong Linux and Python experience * Exceptional communication skills and the ability to collaborate effectively to solve complex problems * Excellent problem-solving, analytical and diagnostic skills * Deep knowledge of scan, DFT, JTAG and trace infrastructure * Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies and system-level debug techniques * Ability to work independently on technically complex debug and validation activities across hardware, firmware and software domains DESIRABLE * Understanding of DFT flows from insertion through post-silicon validation * Experience developing tooling for parsing and analysing debug data, including scan dump parsing * Driver-level experience with one or more of the following technologies: * PCIe * Ethernet * Memory technologies including LPDDR, DDR and HBM * Peripheral interfaces such as I2C, I3C and SPI * Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB and STM * Good knowledge of mixed-signal building blocks such as PLLs, high-speed PHYs and IC control/communication protocols * Experience with Arm CPU architectures, system IP and associated debug tooling * Experience with AMBA protocols * Understanding of ML applications and associated workloads * Experience in characterization, failure analysis, test development, statistical analysis and customer support

Graphcore

ABOUT US Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. JOB SUMMARY Reporting to senior leadership within Architecture and Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness. This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. THE TEAM The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems. The team works across the full product lifecycle, supporting first silicon bring-up, subsystem validation, system integration and production readiness activities. Engineers collaborate closely with hardware, firmware, software and systems teams to investigate complex failures, develop debug methodologies and improve validation infrastructure. RESPONSIBILITIES AND DUTIES * Lead post-silicon debug and validation activities for AI compute silicon and platform technologies * Contribute to debug and validation activities across multiple projects and milestones * Drive prioritisation, planning and execution of debug and validation activities across multiple projects and milestones * Investigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validation * Develop structured debug methodologies and failure analysis processes to improve issue resolution efficiency * Collaborate closely with architecture, RTL, firmware, software and systems engineering teams to identify root causes and implement corrective actions * Drive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditions * Develop and enhance automated debug, regression and validation infrastructure using Python and related technologies * Analyse logs, traces, telemetry and hardware data to isolate and characterize system failures and performance issues * Support development of validation tests, debug tooling and custom diagnostics to improve coverage and observability * Define validation metrics, debug workflows and reporting standards to ensure consistent and repeatable analysis * Drive continuous improvement of debug processes, validation methodologies and engineering workflows * Communicate technical risks, status and recommendations clearly to engineering leadership and cross-functional stakeholders * Support silicon readiness reviews and contribute to product quality and release decisions * Contribute to continuous improvement of debug methodologies, validation infrastructure and engineering workflows CANDIDATE PROFILE ESSENTIAL: * Strong experience in bare metal environments * Good knowledge of SoC and platform architectures * Expertise in debug infrastructure and post-silicon debug methodologies * Strong programming skills in Python, C, or debug scripting languages such as CMM * Highly motivated self-starter with a collaborative and team-oriented approach * Ability to work across teams and programming languages to identify root causes of deep and complex issues * Experience of the post-silicon validation process applied in digital ASIC environments * Strong Linux and Python experience * Exceptional communication skills and the ability to collaborate effectively to solve complex problems * Excellent problem-solving, analytical and diagnostic skills * Deep knowledge of scan, DFT, JTAG and trace infrastructure * Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies and system-level debug techniques * Ability to work independently on technically complex debug and validation activities across hardware, firmware and software domains DESIRABLE * Understanding of DFT flows from insertion through post-silicon validation * Experience developing tooling for parsing and analysing debug data, including scan dump parsing * Driver-level experience with one or more of the following technologies: * PCIe * Ethernet * Memory technologies including LPDDR, DDR and HBM * Peripheral interfaces such as I2C, I3C and SPI * Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB and STM * Good knowledge of mixed-signal building blocks such as PLLs, high-speed PHYs and IC control/communication protocols * Experience with Arm CPU architectures, system IP and associated debug tooling * Experience with AMBA protocols * Understanding of ML applications and associated workloads * Experience in characterization, failure analysis, test development, statistical analysis and customer support

Quantum Motion

ABOUT THE ROLE AND TEAM Quantum Motion is a fast-growing quantum computing start-up based in London. We are developing quantum processors based on industrial-grade silicon chips, with the potential to radically transform computing power in areas such as materials modelling, medicine, artificial intelligence and more. We have recently moved into a new office in Islington with state of the art cryogenic facilities and have an outstanding interdisciplinary team spanning quantum physics to IC design. Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times, and our technology breakthroughs have been featured in The Telegraph, BBC and the New Statesman. Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors, and we have recently closed our Series C funding of $160 million. We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology. Our team of 100+ is based in Oxford and London, with a centre of mass in our Islington lab. OUR TEAM The IC Team is responsible for the design and test of the integrated circuits which operate at deep-cryogenic temperatures and interact with the qubits. This role is a unique chance to work at the bleeding edge of technology development where you will measure, optimise, and analyse the performance of innovative circuits to tackle the engineering challenge of implementing a large-scale quantum computer in silicon. This is a rare and exciting opportunity to be an early employee at a start-up shaping the future of quantum computing. There are vast opportunities for professional growth and to make an impact within the company.  FUNCTIONS OF THE ROLE * Design and verification of continuous-time and discrete-time circuits like amplifiers, filters, high accuracy and high performance data-converters in CMOS technology. * Working with layout team on layout of Analogue and Mixed-Signal blocks * Supporting post-silicon setting up and debugging to evaluate the Performance of the IC * Collaborate with cross-functional teams, including the RF IC Design team, the IC Validation team as well as the Quantum physics team to achieve the project goals. * Documenting own work and contribute in design reviews EXPERIENCE - ESSENTIALS * Solid understanding of Analogue and Mixed-Signal CMOS IC design  * Experience in design of Analogue integrated circuit with silicon-proven results * Familiar with design of Switched-Capacitor circuits and Data Converters in CMOS technology * Strong analytical and problem-solving skills with a high-level of self-management and self-motivation * Familiar with design and verification CAD tools. * Experience in Layout and design strategy EXPERIENCE - DESIRABLE * Experience in design of ADCs and DACs for high-frequency, high-performance or low-power applications.  * Experience in clock generation circuits and PLL * Knowledge of CMOS fabrication technology * Familiar with Cryogenic CMOS design  * knowledge of Verilog, Verilog-A  or Verilog-AMS * Knowledge of MATLAB * Knowledge of DSP and communication system BENEFITS * Be part of a creative, world-leading team * Competitive salary and share options scheme * Contributory pension scheme * Group private medical insurance scheme * Life Assurance * Cycle-to-work Scheme  * Central London location EEO STATEMENT Quantum Motion is committed to providing equal employment opportunity and does not discriminate based on age, sex, sexual orientation, gender identity, race, colour, religion, disability status, marital status, pregnancy, gender reassignment or any other protected characteristics covered by the Equality Act 2010