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MASTER THESIS OPPORTUNITIES

Kvaser AB
  • OrtÅre
  • OmfattningHeltid
  • Sista ansökan29 dagar kvar
  • Publicerad13 nov.

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MASTER THESIS: CANtegrity: CAN FD CAN-bit validation test

Originally, CAN was a computer network using low bit rate where Signal Integrity was not a problem because the signal’s symbol

time was low compared to signal delay in the network. The arbitration rule demanded the bit-length to be almost 4 times the signal

delay over the network. This limitation, implied by the arbitration rule, resulted in bit rates low enough to prevent the

occurrence of signal integrity problems, even if impedances were not well matched. With the introduction of CAN-FD it became

possible to increase the bitrate, thereby becoming more sensitive to impedance variation. The configuration of the CAN-bit, which

is important also for CAN-CC (Can Classic), became even more important when using the complex bitrate switch in CAN FD. The first

problem is to secure that all installed units in the network have a correct CAN-bit configuration. This is complex because the

setting depends not only on the units themselves but also on the clock variations and on the signal delay to all other installed

units. Added to this, it is necessary to understand the signal integrity problem caused by the higher bitrate. By having full

control of the configuration in every installed unit, it is possible to reduce the problem to a minimum.

This master thesis is about developing a test function that can be used to determine the CAN-bit parameters for a CAN network

{TQ-length (ns), number of TQ in the CAN-bit, number of TQ to the Sample point, number if TQ in the SJW}.

The first task is to develop an FPGA logic in Verilog that generates a specific test pattern. This is to be included in the

CANtegrity CAN-FD IP that is used in Kvaser’s hardware. In the test, the signal resulting from the generated test pattern will be

recorded by test software that based on the recorded data calculates the CAN-bit parameters in the unit during the performed test.

This test is carried out with only one unit installed. The main part of the thesis work is the software that searches for pattern

in the recording. This is not time critical so the software can be some sort of high-level language (Python).

If it fits into the time frame, the next task will be to do the same using two units connected to the common CAN-bus. The problem

here is that both connected units could respond concurrently which can make the calculation or analysis more complicated.

The ultimate solution is to run the test on a CAN-bus with N nodes. It is obvious that it is necessary to first complete the test

for N=1 and N=2 before this part of the task is started. In this case it is expected to also measure the distance (in nanoseconds)

to all installed nodes. Kvaser already has a software that can fingerprint every CAN-frame and it is thereby possible to find out

how many different transmitters that are connected to the CAN-bus. This knowledge makes it possible to focus the analysis on each

transmitter and based on the transmitting CAN controller behaviour obtain the distance to the unit.

Author: Kent Lennartsson

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Generic scenario simulator with a Digital Twin approach

A master thesis for two students Radio devices for communication are often exposed to highly dynamic environments, whether it

concerns the systems employing the radio devices or the physical environment in which the radio devices move, thereby causing

significant changes in propagation conditions or changed levels of interference from various emitters and noise sources.

Moreover, radio links may be part of a system comprising multiple radio devices which implies a complex interrelation between the

radio devices and hence very complex scenarios, difficult to test, especially repetitively. The latter would be desirable to

enable trouble shooting and studying of specific situations to draw valuable conclusions from the behaviour of the radio system.

Computer based simulations have the advantages of speeding up the process of validation, at the same time providing statistical

confidence.

To cope with dynamic environments, a radio system needs to have dynamic properties too, whether realized as rules based algorithms

or simpler regulating control processes. The dynamic properties could e.g. be about optimizing the link capacity in different

directions, changing modulation and transmit power or adapting the set of employed frequencies. The radio devices’ abilities to

become aware of this dynamic environment may be possible to different degrees, from simple link quality estimation and sensing of

available frequencies to more advanced methods where the signals are analysed in various ways.

This thesis work is about exploring models for a generic scenario simulator that can be used to try out various dynamic algorithms

to be employed in certain given scenarios. The scenarios may be based on recorded data exchanges from real physical set-ups or on

assumptions of their behaviour. Scenarios may also be based on tracked or assumed movements of radio devices in an area for which

the link qualities will be established by means of special analysis tools not part of the thesis work. This includes different

means to represent the awareness of the dynamic environment.

The scenario simulator should be designed as a “digital twin” to an existing physical simulator consisting of up to seven pairs of

radio devices and two sources of interference in which the radio propagation conditions and the load with respect to generated

messages can be dynamically changed. The scenario simulator shall implement the dynamic algorithms autonomously acting on various

stimuli, a digital representation of the awareness information to be the outcome from a transformation of information provided by

the analysis of real physical scenarios.

The scenario simulator provides the ability to alter the dynamic algorithms to a great extent and to design advanced behavioural

models for autonomous acting. These algorithms should allow for incorporation into the control logic of the radio devices to

enable validation in the physical scenario simulator (a test rig). This requires a time base implementation that allows adaptation

to real time operative systems.

Author: Anders Bäckman

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Multidrop network analysis and simulation

The goal is to have a program that will help users to understand what you can do with a multidrop network without jeopardizing the

signal integrity. When bit-rate increases, it is necessary to consider the signal integrity of the cable layout. There are a lot

of tools and books covering Radio Frequency (RF) signals for a narrow band signal that can be found. It is however a little more

complicated for digital data communication where the energy is spread over a several frequencies.

Even for digital signals there are several books on the subject and instruments to analyze the problem. There are several

suppliers of instruments working both in the frequency and time domain that handle this problem, but they assume a Point-to-Point

transmission line at a relatively high frequency. No books exist that discuss the complex multidrop communication used in CAN,

10BASE-T1S or 802.3dg. The frequency range is relatively low (below200 MHz) but the transmission line is a very complex network

with multiple drop lines to the transceiver circuits. For such complex networks it is not possible to use TDR (Time Domain

Reflectometer) and VNA (Vector Network Analyzer) in the same way as they are used for a Point-to-Point network.

This problem could be solved by the generic program ADS (Advance Design Systems) provided by Keysight which is designed to solve

any problem involving both high bandwidth and frequency. This is a complex and expensive tool. What we need is a program that

solves only our specific problem that is relatively simple but involves a lot of calculation.

Handling this task will demand knowledge about S-parameters and programming (Python) to mathematically process the S-parameters.

The suggestion is to obtain adequate understanding of the problem by carefully studying the information found in the book

“S-parameters for Signal Integrity” by Peter J. Pupalaikis ISBN 978-1-108-48996-6. This book has reference to a software package

(SignalIntegrity) written in Python that it is suggested to be used as the platform for this program.

Instead of modelling the CAN/802.3dg multidrop networks for simulation in Spice, it is suggested to build the layout with

S-parameter blocks to describe the multi-drop network. This will make it possible analyze the system’s expected signal integrity

without having to know every minute detail. It is thereby possible to define the allowed S-parameters that a node can have and use

this as boundaries for the S-parameters of the nodes to be installed.

It can also be possible to measure the S-parameters for the installed nodes and use that as input to check if the system can

provide the necessary signal integrity.

Author: Kent Lennartsson

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Scalable two-layered computer architecture

A master thesis for two students

Layering of communication protocols is an important pre-requisite for standardised communication systems. When it comes to radio

technology, this may be considered even more important. This is because changes to radio functionality may require very costly

re-certification of a radio device. With a layered approach, it could be possible to isolate its radio functions to a degree that

ensures that the impact of changes to the radio device do not impact the performance and behaviour from a certification aspect.

Also, the extent of regression tests and verification is reduced if it is possible to limit any change to a certain layer.

The desired situation would be to contain the software related to the radio functions in a separate processing unit. The radio

functions would thereby be regarded as hierarchically lower and closer to the physical layer which is sometimes referred to as

Media Access layer (MAC). The radio functions would thereby be accessible via a clearly defined interface to a radio transceiver

and a suitable Application Protocol Interface (API). This layered approach also provides scalability in the sense that it would be

possible with multiple radio transceivers connected to one radio controller.

This thesis work is about exploring methods to create a layered architecture for a radio solution which could be a combined radio

controller and radio transceiver or a distributed more complex constellation with multiple radio transceivers, all connected to

the same radio controller which runs multiple processes in a co-ordinated way. This co-ordination would be of interest in

solutions where multiple transceivers cannot be allowed to transmit simultaneously. Hence, the characteristics of the system,

particularly that of the mentioned interface, is highly important when it comes to synchronization of multiple radio transceivers

and their processing units. Latency is another important property of the interface with its protocol in that it will have a direct

impact on the delay characteristics of a radio connection, especially in cases where the radio controller interfaces to multiple

radio transceivers that are to be employed simultaneously.

The layered architecture shall be implemented in a set-up consisting of a processor board representing the radio controller and

another processor board that represents the radio functionality. The latter should be connected to a radio transceiver. A suitable

interface (including API) shall be implemented to convey control information between the radio controller and the processor of the

radio transceiver which is emulating the radio chip. This set-up should be modifiable in such a way that the emulation can be

replaced by a connection to a radio chip, thereby enabling the set-up to communicate with an existing radio device based on the

traditional single processor architecture.

The thesis work includes separating an existing but limited software into a two layered architecture which is supposed to be

interoperable with the existing software.

Author: Anders Bäckman

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Time synchronization by gPTP

The NTP (Network Time Protocol) is well known in the LAN (Local Area Network) and internet connections. For a small LAN, its

precision varies from a few milliseconds down to a 1 millisecond. For Ethernet there is standard IEEE1588 which is the basis for

PTP (Precision Time Protocol) that provides a sub microsecond precision. The problem with this standard is the assumption that the

latency is constant over time and symmetric. Moreover, it is not an integrated part in IEEE802 (Ethernet) standard. This has been

solved in the standard IEEE802.1AS, named gPTP (generalized Precision Time Protocol) that requires special Ethernet hardware but

that provides good precision over time independently of hardware supplier. The IEEE802.1AS standard is also the time base for TSN

(Time Sensitive Networking) which is a hardware function that with several different means secures the communication latency, that

the communication is not exhausted, and by that ensures that the most important information has priority.

When logging data, it is important to have the same time base for all sources of data. For our USB-interfaces that problem is

solved with Kvaser’s MagiSync.technology.

Some products are based on Ethernet where MagiSync is not directly applicable. For that reason, it is of interest to understand

how it would be possible to use gPTP in Kvaser’s products.

The goal of the master thesis is to develop software for hardware to be selected that in combination with the hardware provide

functions as described IEEE802.1AS.

The work will start by studying the IEEE802.1AS to understand the function and which hardware will be required to obtain a working

solution. It will be necessary to find an already existing hardware because there will be no time to design and produce any

specific hardware. As a worst case, it could be necessary to design an FPGA logic that can provide the necessary hardware

functionality to obtain a working solution.

The thesis work requires some knowledge about software preferably RUST or C. Should no suitable hardware be found it would be

necessary with knowledge about Verilog that is used to emulate hardware.

Author: Kent Lennartsson